Technical Articles
Embedded engineering blog
277 articles organised by roadmap branch and topic. Reading a topic’s article is how you mark it learned.
Analog Electronics55 articles
- Bode Plot: Magnitude and Phase vs. FrequencyBode Plot: Magnitude and Phase vs. FrequencyBode Plot: Magnitude and Phase vs. Frequency What a Bode Plot Is A Bode plot is a graphical representation of a linear, time-invariant LTI system's frequency response. It splits t...6 min read
- Capacitor: Charge, Energy, V-I Relationship (I = C dV/dt)Capacitor: Charge, Energy, V-I Relationship (I = C dV/dt)How Q = CV, W = ½CV², and I = C dV/dt govern capacitor behavior — with a fully checked constant-current charging example and design implications.6 min read
- Circuit Sensitivity Analysis: ∂H/∂ComponentCircuit Sensitivity Analysis: ∂H/∂ComponentHow to quantify and combine component tolerances into predicted circuit variation using ∂H/∂x — with a worked RC filter example and design implications.5 min read
- Decibel (dB): Voltage, Current, and Power RatiosDecibel (dB): Voltage, Current, and Power RatiosHow the 10·log₁₀ and 20·log₁₀ decibel formulas relate power, voltage, and current ratios — and where the impedance-matching assumption can trip you up.7 min read
- Elmore Delay Model for RC InterconnectsElmore Delay Model for RC InterconnectsHow to estimate RC interconnect delay with a closed-form sum instead of full SPICE — the model behind buffer insertion and static timing analysis.6 min read
- Fourier Series: Harmonic Decomposition of SignalsFourier Series: Harmonic Decomposition of SignalsHow periodic signals break into sinusoidal harmonics, with the square-wave series worked in full and the design impact on EMI, PWM filtering, and THD.5 min read
- Impedance (Z), Admittance (Y), Reactance (X)Impedance (Z), Admittance (Y), Reactance (X)How impedance, admittance, and reactance extend Ohm's Law to AC circuits with complex numbers, worked with a full series RL example and Z↔Y conversion.6 min read
- Inductor: Flux, Energy, V-I Relationship (V = L dI/dt)Inductor: Flux, Energy, V-I Relationship (V = L dI/dt)How inductors store energy in a magnetic field, why V = L·dI/dt governs their behavior, and why interrupting inductor current safely requires a flyback path.7 min read
- Kirchhoff's Current Law (KCL) and Node AnalysisKirchhoff's Current Law (KCL) and Node AnalysisA quantitative walkthrough of KCL and node analysis — supernodes, a fully worked and verified example, and why this method underlies every SPICE simulator.7 min read
- LTspice: Schematic Entry and Simulation BasicsLTspice: Schematic Entry and Simulation BasicsA practical walkthrough of LTspice schematic entry, SPICE analysis directives, and a worked RC step-response example — the baseline skill for validating any analog circuit before prototyping.6 min read
- Laplace Transform for Circuit AnalysisLaplace Transform for Circuit AnalysisHow the Laplace transform turns RLC differential equations into algebra, unifies transient and AC analysis, and produces the transfer function H(s) used throughout circuit design.6 min read
- Lumped vs. Distributed Element CircuitsLumped vs. Distributed Element CircuitsWhen do wires stop being "just wires"? A quantitative look at the λ/10 rule that separates lumped circuit theory from transmission-line behavior.6 min read
- Maximum Power Transfer Theorem (RL = RS)Maximum Power Transfer Theorem (RL = RS)Derives the R_L = R_S condition for maximum power transfer, verifies it with a worked example, and explains why matched loading sacrifices efficiency to 50%.6 min read
- Millman's Theorem for Parallel Voltage SourcesMillman's Theorem for Parallel Voltage SourcesMillman's theorem collapses any set of parallel voltage sources with series impedances into one equivalent node voltage — derived from KCL, verified with a worked example.6 min read
- Non-Ideal Components: Parasitic R, L, C EffectsNon-Ideal Components: Parasitic R, L, C EffectsReal resistors, capacitors, and inductors act like small RLC networks — this article shows where each parasitic dominates and how to design around it.5 min read
- Ohm's Law: V = IR and Power Dissipation P = IVOhm's Law: V = IR and Power Dissipation P = IVA rigorous walk through V = IR and P = IV — where the ideal resistor model holds, where it breaks, and a fully worked LED resistor sizing example with power checks.7 min read
- Phasor Representation and Complex ImpedancePhasor Representation and Complex ImpedancePhasors turn sinusoidal steady-state circuits into complex algebra, and impedance lets Ohm's law, dividers, and KVL/KCL work directly on capacitors and inductors.6 min read
- RC Circuit: Time Constant τ = RC, Charging/DischargingRC Circuit: Time Constant τ = RC, Charging/DischargingHow the RC time constant τ = RC governs capacitor charging and discharging, with the exponential equations, a worked example, and design sizing rules.5 min read
- RL Circuit: Time Constant τ = L/R, Transient ResponseRL Circuit: Time Constant τ = L/R, Transient ResponseHow the L/R time constant governs current rise and decay in RL circuits, why inductive kickback happens, and how to size snubbers and flyback protection.6 min read
- RLC Parallel Circuit: Anti-Resonance and Impedance PeakRLC Parallel Circuit: Anti-Resonance and Impedance PeakWhy a parallel RLC tank shows maximum impedance at resonance instead of minimum, how Q and bandwidth invert from the series case, and why circulating tank currents can dwarf the source current.6 min read
- RLC Series Circuit: Resonance, Q-Factor, BandwidthRLC Series Circuit: Resonance, Q-Factor, BandwidthHow resonant frequency, Q-factor, and bandwidth relate in a series RLC circuit, with the full derivation and a worked numerical design example.6 min read
- Reciprocity Theorem and Its ApplicationsReciprocity Theorem and Its ApplicationsReciprocity lets you swap a source and a measurement point in any linear passive network and get the same result — a shortcut used in antenna, RF, and audio design.6 min read
- SPICE Simulation: DC, AC, Transient AnalysisSPICE Simulation: DC, AC, Transient AnalysisHow SPICE's DC, AC, and transient engines actually solve a circuit, what each one can and can't show, and a worked RC example checked three ways.7 min read
- Series and Parallel Resistor CombinationsSeries and Parallel Resistor CombinationsHow to reduce series and parallel resistor networks to a single equivalent value, with worked examples, power-dissipation gotchas, and when the shortcuts don't apply.6 min read
- Signal Ground, Chassis Ground, and Earth GroundSignal Ground, Chassis Ground, and Earth GroundSignal, chassis, and earth ground are three distinct nodes with different impedances and jobs — confusing them causes hum loops, EMI failures, and shock hazards.6 min read
- Skin Effect and High-Frequency Conductor LossSkin Effect and High-Frequency Conductor LossWhy AC resistance rises with frequency, how skin depth is calculated, and a worked example showing a 4x resistance increase in copper wire at 1 MHz.6 min read
- Superposition Theorem for Linear CircuitsSuperposition Theorem for Linear CircuitsHow to solve multi-source linear circuits by analyzing one source at a time, why dependent sources can't be zeroed, and why power breaks the rule.7 min read
- Thevenin's Theorem: Equivalent Voltage and ResistanceThevenin's Theorem: Equivalent Voltage and ResistanceLearn how to collapse any linear resistive network into a single voltage source and series resistor — with a fully worked, cross-checked example.7 min read
- Transfer Function H(s) and Poles/ZerosTransfer Function H(s) and Poles/ZerosHow H(s) encodes a circuit's entire dynamic behavior, and why pole/zero locations on the s-plane predict stability, resonance, and transient response.7 min read
- Transmission Line Theory: Characteristic Impedance Z0Transmission Line Theory: Characteristic Impedance Z0How distributed L and C on a real interconnect define Z0 = √(L'/C'), why it governs reflections, and how to size traces to hit 50 Ω or 100 Ω targets.8 min read
- Two-Port Network Parameters: Z, Y, H, ABCDTwo-Port Network Parameters: Z, Y, H, ABCDHow Z, Y, H, and ABCD parameters characterize any linear two-port network, when to use each, and how to cascade stages or convert between the four representations.6 min read
- Wye (Y) and Delta (Δ) Network TransformationWye (Y) and Delta (Δ) Network TransformationHow to convert between Wye and Delta resistor networks with exact formulas, a worked bridge-circuit example, and checks that confirm the equivalence.6 min read
- BJT Current Gain (β, hFE) and Base Current ControlBJT Current Gain (β, hFE) and Base Current ControlHow β (hFE) links base and collector current in a BJT, why it varies 2–3× across temperature and parts, and how to size base drive that survives the spread.6 min read
- BJT Frequency Response: fT and fmaxBJT Frequency Response: fT and fmaxHow Cπ, Cμ, and base resistance set the speed limits of a BJT — deriving fT and fmax from the hybrid-π model with a full worked GHz-range example.6 min read
- BJT Operating Regions: Active, Saturation, Cutoff, BreakdownBJT Operating Regions: Active, Saturation, Cutoff, BreakdownHow the bias state of a BJT's two junctions defines its four operating regions — and how to verify by calculation which one a real circuit sits in.7 min read
- Crystal Structure: Silicon Lattice and Covalent BondsCrystal Structure: Silicon Lattice and Covalent BondsHow silicon's tetrahedral covalent bonds form the diamond-cubic lattice — and why that geometry underlies doping, bandgap, and every transistor I-V curve.6 min read
- Depletion Region: Width, Electric Field, Space ChargeDepletion Region: Width, Electric Field, Space ChargeHow diffusion creates a carrier-free space charge region at a p-n junction, and how to calculate its width, peak field, and built-in potential.7 min read
- Diode I-V Characteristic: Shockley EquationDiode I-V Characteristic: Shockley EquationA quantitative walkthrough of the Shockley diode equation — forward voltage, temperature drift, and small-signal resistance — with a fully checked worked example.5 min read
- Early Effect: VA, Output Resistance (ro) in BJTEarly Effect: VA, Output Resistance (ro) in BJTHow base-width modulation gives every BJT a finite output resistance ro ≈ VA/IC, and why that single parameter caps single-stage voltage gain.6 min read
- IGBT: Structure, Characteristics, and ApplicationsIGBT: Structure, Characteristics, and ApplicationsHow the IGBT merges a MOSFET gate with a bipolar output stage, why its turn-off tail limits switching frequency, and where it beats power MOSFETs.8 min read
- MOSFET Short-Channel Effects: DIBL, Velocity SaturationMOSFET Short-Channel Effects: DIBL, Velocity SaturationHow DIBL and velocity saturation break the long-channel square-law MOSFET model — with a worked example comparing predicted vs. real short-channel drive current.7 min read
- MOSFET as Switch: On-Resistance RDS(on) and Gate Charge QgMOSFET as Switch: On-Resistance RDS(on) and Gate Charge QgHow R_DS(on) sets conduction loss and Q_g sets switching loss and drive current — with worked calculations and the trade-off that governs MOSFET selection.7 min read
- NMOS/PMOS I-V Characteristics: Triode and Saturation RegionsNMOS/PMOS I-V Characteristics: Triode and Saturation RegionsThe square-law equations that separate triode from saturation in NMOS and PMOS devices, worked through a numeric example and checked at the region boundary.6 min read
- PIN Diode: Microwave Switch and Attenuator ApplicationsPIN Diode: Microwave Switch and Attenuator ApplicationsHow a lightly-doped I-region turns a simple p-n junction into a bias-controlled RF resistor — the basis for microwave switches and variable attenuators.7 min read
- Photodiode: Photovoltaic and Photoconductive ModesPhotodiode: Photovoltaic and Photoconductive ModesPhotodiodes can run unbiased (photovoltaic) or reverse-biased (photoconductive) — the choice sets your noise floor, bandwidth, and linearity.6 min read
- Power MOSFET: SOA (Safe Operating Area) and BreakdownPower MOSFET: SOA (Safe Operating Area) and BreakdownHow to read a power MOSFET's SOA curve, why pulse width changes the safe boundary, and how to check a fault transient against both power and thermal limits.7 min read
- Reverse Bias: Leakage Current, Breakdown MechanismsReverse Bias: Leakage Current, Breakdown MechanismsReverse bias current is never truly zero, and breakdown voltage is a function of temperature and doping, not a fixed limit — here's the physics and the design math.7 min read
- Schottky Diode: Metal-Semiconductor Junction, Low VFSchottky Diode: Metal-Semiconductor Junction, Low VFWhy the metal-semiconductor junction gives Schottky diodes lower forward drop and near-zero reverse recovery — with the physics and a converter loss example.6 min read
- SiC MOSFET: Wide Bandgap Advantages for PowerSiC MOSFET: Wide Bandgap Advantages for PowerHow SiC's wider bandgap and higher critical field translate into 5–10× lower on-resistance, faster switching, and higher junction temperatures than silicon.6 min read
- Transistor Data Sheet Interpretation: Key ParametersTransistor Data Sheet Interpretation: Key ParametersA practical guide to reading BJT and MOSFET data sheets — separating absolute maximums from guaranteed characteristics, and using the curves that tables leave out.7 min read
- Triac and Diac: AC Power ControlTriac and Diac: AC Power ControlHow a triac and its diac trigger form phase-control AC dimmers and switches — the four triggering quadrants, RC firing-angle math, and design pitfalls.9 min read
- Varactor Diode: Junction Capacitance vs. Voltage (CV Curve)Varactor Diode: Junction Capacitance vs. Voltage (CV Curve)How reverse-bias depletion width sets varactor capacitance, why the grading coefficient m determines VCO tuning linearity, and a worked CV calculation.5 min read
- Zener Diode Voltage Regulator Circuit DesignZener Diode Voltage Regulator Circuit DesignHow to size the series resistor and check worst-case current in a zener voltage regulator, with a fully worked design and buffered-zener variant for higher load current.6 min read
- Difference Amplifier: CMRR and Resistor MatchingDifference Amplifier: CMRR and Resistor MatchingWhy the single op-amp difference amplifier's CMRR is set almost entirely by resistor matching, with a worked example showing how 1% resistors can swamp a small differential signal.7 min read
- Gain-Bandwidth Product (GBW): 1 MHz, 10 MHz DevicesGain-Bandwidth Product (GBW): 1 MHz vs 10 MHzHow gain-bandwidth product fixes the trade-off between gain and bandwidth, and when a 10 MHz op-amp is worth the extra power and noise over a 1 MHz part.10 min read
Digital Electronics9 articles
- Barrel Shifter: Combinational Shift by N BitsBarrel Shifter: Combinational Shift by N BitsHow barrel shifters use cascaded multiplexer stages to shift or rotate an N-bit word in one cycle, and the area, timing, and power trade-offs involved.8 min read
- Logic Levels: VIL, VIH, VOL, VOH and Noise MarginsLogic Levels: VIL, VIH, VOL, VOH & Noise MarginsA practical guide to the voltage thresholds and noise margins that determine whether digital signals are read correctly or fail intermittently in the field.10 min read
- Shift Register: Serial-In Serial-Out (SISO), SIPO, PISO, PIPOShift Registers: SISO, SIPO, PISO, PIPO ExplainedA clear walkthrough of the four shift register architectures—SISO, SIPO, PISO, PIPO—covering data flow, control signals, timing pitfalls, and selection criteria.10 min read
- Timing Closure: Critical Path, Register RetimingTiming Closure: Critical Path & Register RetimingHow to find the critical path in an FPGA design and use register retiming to pass real static timing analysis, not just simulation.12 min read
- Body Biasing: Forward Body Bias (FBB) and RBB for LeakageBody Biasing: FBB and RBB for Leakage ControlHow dynamic body biasing trades threshold voltage against leakage and speed, and why RBB beats power-off when state retention matters.9 min read
- Dynamic Power: P = α C V² f (Activity, Cap, Voltage, Freq)Dynamic Power Formula: P = αCV²f ExplainedA breakdown of the dynamic power formula P = αCV²f, showing why voltage scaling dominates power optimization and how activity factor shapes real-world chip power budgets.8 min read
- Junction Leakage: Reverse-Biased Diode CurrentJunction Leakage in Reverse-Biased DiodesWhy reverse-biased junctions never fully turn off, how junction leakage compares to subthreshold and gate leakage, and which biasing techniques actually suppress it.11 min read
- Subthreshold Leakage: Exponential Dependency on VTSubthreshold Leakage: VT Exponential DependencyA 50 mV drop in threshold voltage can multiply subthreshold leakage several-fold. Here's the physics behind the exponential law and the design techniques that keep it in check.10 min read
- Static Timing Analysis (STA): PrimeTime / TempusStatic Timing Analysis: PrimeTime & TempusA practical comparison of PrimeTime and Tempus for exhaustive timing closure, covering Liberty corners, setup/hold detection, clock skew, SDC exceptions, and ECO flows.11 min read
Embedded Systems42 articles
- ADC Key Specs: Resolution, ENOB, INL, DNL, SNRADC Key Specs: Resolution, ENOB, INL, DNL, SNRWhy ADC Specs Matter for Embedded Design Moving beyond bit count: what specs really tell you A "12-bit ADC" tells you almost nothing about how well it will measure your signal. Re...8 min read
- Analog Comparator: Hysteresis and Wake-Up ApplicationAnalog Comparator: Hysteresis & Wake-Up DesignHow to use analog comparators with hysteresis to build ultra-low-power wake-up and threshold-detection circuits without touching the ADC or CPU.12 min read
- Key Provisioning: Certificate Injection at ManufacturingCertificate Injection at ManufacturingHow embedded manufacturing lines inject and protect device certificates, and how bootloaders verify them to establish a hardware root of trust.10 min read
- Pipeline Stages: Fetch, Decode, Execute, Memory, Write-BackCPU Pipeline Stages: Fetch Through Write-BackA breakdown of Fetch, Decode, Execute, Memory, and Write-Back, how hazards stall the pipeline, and the code and memory patterns that keep embedded CPUs running at full throughput.9 min read
- CMSIS-NN: ARM-Optimized Kernel Library for Cortex-MCMSIS-NN: ARM-Optimized Kernel Library for Cortex-MHow ARM's CMSIS-NN library turns quantized int8 CNN layers into SIMD/DSP-instruction kernels on Cortex-M, with the math and measured speedups behind it.6 min read
- Camera Interface: DVP (Digital Video Port) and MIPI CSI-2Camera Interface: DVP (Digital Video Port) and MIPI CSI-2A quantitative comparison of parallel DVP and serial MIPI CSI-2 camera interfaces — bandwidth limits, pin cost, and how to pick the right one by the numbers.7 min read
- Color Space Conversion: RGB888 → RGB565 → GrayscaleColor Space Conversion: RGB888 → RGB565 → GrayscaleHow and why embedded vision pipelines downcast RGB888 to RGB565 for displays and to grayscale for CNN/CV input — with bit-packing math, fixed-point luma, and error analysis.8 min read
- Continual / Incremental Learning on Embedded DevicesContinual / Incremental Learning on Embedded DevicesHow MCUs and NPUs update models in the field without catastrophic forgetting: EWC, replay, and frozen-backbone prototype learning, with a real memory budget worked example.7 min read
- EThos-U55 / U65: Arm ML Processor for Cortex-M SystemsEThos-U55 / U65: Arm ML Processor for Cortex-M SystemsHow Arm's Ethos-U55/U65 microNPUs offload CNN inference from Cortex-M cores, how Vela compiles and partitions models, and how to size real throughput and power.7 min read
- Edge AI Overview: Inference at the Device vs. CloudEdge AI Overview: Inference at the Device vs. CloudA quantitative comparison of on-device and cloud inference — latency budgets, power draw, model-size ceilings, and a worked wake-word power example.7 min read
- Edge Impulse: Data Collection, Training, Deployment to MCUEdge Impulse: Data Collection, Training, Deployment to MCUA practical walkthrough of Edge Impulse's data-to-deployment pipeline: what to get right in data collection, where the DSP block burns cycles, and how EON affects MCU RAM budgets.8 min read
- Embedded OpenCV: ARM Neon OptimizationEmbedded OpenCV: ARM Neon OptimizationHow ARM NEON accelerates OpenCV's core kernels, why real speedups land at 3–8× instead of the theoretical 16×, and how to verify NEON is actually active in your build.6 min read
- Face Detection on MCU: Haar Cascade, MobileNet-SSDFace Detection on MCU: Haar Cascade, MobileNet-SSDCompares Haar cascades and quantized MobileNet-SSD for on-MCU face detection, with the compute, RAM, and latency math behind each approach in detail.7 min read
- Federated Learning on MCU: Privacy-Preserving On-DeviceFederated Learning on MCU: Privacy-Preserving On-DeviceHow to fit federated learning's train-locally, share-only-updates pattern onto Cortex-M budgets: what to train, what to send, and how to bound privacy leakage.7 min read
- Future Edge AI: RISC-V AI Extensions, Chiplet NPU IntegrationFuture Edge AI: RISC-V AI Extensions, Chiplet NPU IntegrationHow RISC-V vector/custom ISA extensions and chiplet-based NPU integration are replacing fixed-function edge AI accelerators, with a worked bandwidth/energy budget.7 min read
- Gesture Recognition: IMU Data → TFLite Micro InferenceGesture Recognition: IMU Data → TFLite MicroA practical, end-to-end guide to building battery-powered gesture recognition systems: IMU preprocessing, CNN architecture, quantization, and TFLite Micro deployment.10 min read
- Image Preprocessing on MCU: Resize, Crop, NormalizeImage Preprocessing on MCU: Resize, Crop, NormalizeHow resize, crop, and normalize stages on an MCU must exactly mirror training-time preprocessing — and why getting the order or math wrong silently costs accuracy.7 min read
- JPEG Decode on MCU: libjpeg-turbo, STM32 JPEG HW IPJPEG Decode on MCU: libjpeg-turbo, STM32 JPEG HW IPComparing software JPEG decode (libjpeg-turbo on Cortex-M DSP extensions) against STM32's hardware JPEG codec IP, with a worked frame-budget example for a real-time vision pipeline.7 min read
- Keyword Spotting (KWS): DS-CNN on Cortex-M for Wake-WordKeyword Spotting (KWS): DS-CNN on Cortex-M for Wake-WordHow Depthwise-Separable CNNs deliver always-on wake-word detection on Cortex-M MCUs — architecture, MAC/memory sizing, quantization, and a real power budget.6 min read
- Knowledge Distillation: Teacher-Student Model CompressionKnowledge Distillation: Teacher-Student Model CompressionHow training a small student network on a large teacher's soft outputs recovers accuracy that pruning and quantization alone cannot, with a worked keyword-spotting sizing example.6 min read
- MAX78000: Ultra-Low-Power CNN AcceleratorMAX78000: Ultra-Low-Power CNN AcceleratorHow the MAX78000's weight-stationary, in-memory CNN accelerator hits sub-µJ inference — and the SRAM/quantization constraints that shape any model targeting it.6 min read
- MCU AI Frameworks: TensorFlow Lite Micro (TFLite Micro)MCU AI Frameworks: TensorFlow Lite Micro (TFLite Micro)How TensorFlow Lite Micro fits neural nets into KB-scale RAM using a static tensor arena — with the allocation math worked through on a real model.6 min read
- MCU Inference Benchmarks: MLPerf Tiny ResultsMCU Inference Benchmarks: MLPerf Tiny ResultsHow to read MLPerf Tiny's closed vs. open division results correctly, and why energy-delay product — not latency alone — is the metric that predicts real battery life.6 min read
- Memory Optimization: Scratch Buffer, In-Place OperationsMemory Optimization: Scratch Buffer, In-Place OperationsHow to shrink an inference graph's peak RAM by reusing scratch buffers and writing operator outputs in place — the difference between fitting a model and not.7 min read
- Model Deployment Pipeline: CI/CD for Edge AI ModelsModel Deployment Pipeline: CI/CD for Edge AI ModelsHow to build a CI/CD pipeline for edge AI models — data/model versioning, quantized target builds, hardware-in-the-loop gates, and staged OTA rollout.7 min read
- Model Pruning: Weight Magnitude, Structured vs. UnstructuredModel Pruning: Weight Magnitude, Structured vs. UnstructuredHow to shrink a neural network for MCU deployment with weight-magnitude pruning, and why structured pruning — not unstructured — is usually what actually speeds up Cortex-M inference.8 min read
- NDP120 / NDP200: Syntiant Neural Decision ProcessorNDP120 / NDP200: Syntiant Neural Decision ProcessorHow Syntiant's NDP120/NDP200 inference ASICs enable always-on keyword spotting and sensor classification at microwatt power — with a worked battery-life budget.7 min read
- Neuromorphic Computing: Intel Loihi, BrainScaleS BasicsNeuromorphic Computing: Intel Loihi, BrainScaleS BasicsHow spiking neuron models turn Intel Loihi and BrainScaleS into event-driven processors, and when that architecture actually beats a dense NPU on energy.6 min read
- ONNX Runtime for Embedded: Inference on Cortex-AONNX Runtime for Embedded: Inference on Cortex-AHow ONNX Runtime schedules graphs, quantizes, and picks execution providers on Cortex-A Linux boards — with a worked MobileNetV2 latency budget.7 min read
- OTA Update for AI Model: Delta Model Update StrategyOTA Update for AI Model: Delta Model Update StrategyHow delta encoding of weight tensors cuts OTA payloads 10–50× versus full-model transfer, with a worked bandwidth/compression example and safe reconstruction on flash-limited MCUs.7 min read
- Object Detection on MCU: YOLO-Nano, TinyYOLOObject Detection on MCU: YOLO-Nano, TinyYOLOHow TinyYOLO and YOLO-Nano compress object detection to fit Cortex-M SRAM and MAC budgets, with a worked sizing example on an STM32H7-class MCU.6 min read
- OpenMV Cam: Machine Vision on STM32H7OpenMV Cam: Machine Vision on STM32H7How an STM32H7's Cortex-M7 core, DCMI DMA pipeline, and MicroPython stack turn OpenMV Cam into a real-time classical-CV and light-CNN vision platform — and where its limits are.7 min read
- Operator Fusion: Reducing Memory and Compute OverheadOperator Fusion: Reducing Memory and Compute OverheadOperator fusion merges chained ops like Conv+BatchNorm+ReLU into one kernel call, cutting memory traffic and dispatch overhead — often the biggest lever on MCU inference latency.7 min read
- Optical Flow on MCU: Lucas-Kanade for UAV StabilizationOptical Flow on MCU: Lucas-Kanade for UAV StabilizationHow the Lucas-Kanade optical flow algorithm reduces to a cheap 2×2 linear solve per point, and how to fit it into a Cortex-M cycle budget for UAV hover stabilization.7 min read
- Person Detection: MobileNet-v2 on CMSIS-NNPerson Detection: MobileNet-v2 on CMSIS-NNHow MobileNet-v2's inverted-residual blocks and CMSIS-NN's INT8 SIMD kernels combine to run real-time, low-power person detection on a Cortex-M MCU.6 min read
- Post-Training Quantization: FP32 → INT8 Weight ConversionPost-Training Quantization: FP32 → INT8 Weight ConversionHow FP32 weights become INT8 for MCU inference: the scale/zero-point math, per-channel quantization, integer requantization, and why calibration makes or breaks accuracy.6 min read
- PyTorch Mobile: Lightweight Inference on Embedded LinuxPyTorch Mobile: Lightweight Inference on Embedded LinuxHow to export PyTorch models to TorchScript and run them efficiently with LibTorch on Cortex-A Linux, with quantization math and a real latency budget check.7 min read
- Quantization-Aware Training (QAT): Simulated QuantizationQuantization-Aware Training (QAT): Simulated QuantizationHow simulated quantization and the straight-through estimator let a network learn weights that survive INT8 (or lower) rounding, closing the accuracy gap PTQ leaves behind.6 min read
- STM32N6: Neural ART Accelerator on STM32STM32N6: Neural ART Accelerator on STM32How ST's Neural ART NPU on STM32N6 shifts CNN inference from CPU-bound compute to memory-bound pipelines — architecture, toolchain, and a worked throughput estimate.7 min read
- TFLite Micro Workflow: Train → Convert → Quantize → DeployTFLite Micro Workflow: Train → Convert → Quantize → DeployA precise walkthrough of the TFLite Micro pipeline — training in float32, converting to FlatBuffer, INT8 quantization math, and sizing the deployment memory arena.7 min read
- Time-Series Classification: 1D CNN on Sensor DataTime-Series Classification: 1D CNN on Sensor DataHow to size, quantize, and deploy a 1D convolutional network for classifying IMU/vibration sensor windows on Cortex-M, with full MAC and memory budgeting.7 min read
- TinyML Benchmarking: eAI, TinyMLPerf, MLCommonsTinyML Benchmarking: eAI, TinyMLPerf, MLCommonsHow MLPerf Tiny, EEMBC's eAI suite, and MLCommons standardize accuracy, latency, and energy so vendor TOPS claims can actually be compared across silicon.7 min read
Power Electronics3 articles
- Body Diode Reverse Recovery: Qrr, trr and LossesBody Diode Reverse Recovery: Qrr, trr, and LossHow stored charge in a MOSFET's body diode creates reverse recovery current, power loss, and EMI—and how Qrr, trr, dead-time, and diode choice interact.10 min read
- Switching Transients: VDS/VGS Overshoot, RingingSwitching Transients: VDS/VGS Overshoot & RingingWhy VDS and VGS overshoot and ringing happen during hard switching, how to measure them correctly, and which layout and snubber techniques actually reduce stress in production.8 min read
- EMI Shielding: Faraday Cage, Ferrite Bead, Slot AntennaEMI Shielding: Faraday Cage, Ferrite Bead & Slot AntennaA practical guide to the three pillars of EMI shielding—field containment, ferrite absorption, and slot-antenna control—with thermal and compliance trade-offs for power electronics design.10 min read
RF & Wireless6 articles
- Ampere-Maxwell Law: ∇×H = J + ∂D/∂tAmpere-Maxwell Law: EM Wave GenerationHow the Ampere-Maxwell law's displacement current term resolves the gap in classical Ampère's law and underlies every RF propagation and simulation result.10 min read
- Link Budget: EIRP, Path Loss, Sensitivity, MarginLink Budget: EIRP, Path Loss, Sensitivity & MarginMaster the four pillars of link budget analysis—EIRP, path loss, sensitivity, and margin—to predict whether an RF link will close before building hardware.11 min read
- Standing Waves: Nodes and Antinodes of V and IStanding Waves: Voltage & Current Nodes and AntinodesWhy voltage and current peaks never line up on a mismatched transmission line, and how that spatial offset dictates input impedance, VSWR, and matching strategy.10 min read
- Telegrapher's Equations: Voltage and Current WavesTelegrapher's Equations: Voltage & Current WavesA first-principles derivation of the telegrapher's equations, showing how voltage and current become traveling waves on a transmission line and why that changes RF design.10 min read
- VNA Calibration: SOLT, TRL, SOLR, LRM MethodsVNA Calibration: SOLT, TRL, SOLR, LRM MethodsA practical guide to choosing between SOLT, TRL, SOLR, and LRM VNA calibration methods based on connector type, frequency range, and impedance environment.9 min read
- Dynamic Range: Spurious-Free DR, BDR, Linear DRDynamic Range in RF Receivers: SFDR, BDR, Linear DRA breakdown of why receiver datasheets list three different dynamic range numbers, what each one actually measures, and which one determines real-world performance.9 min read
Signal Processing1 article
PCB & Hardware Design4 articles
- Annular Ring: IPC-6012 Minimum Ring RequirementAnnular Ring: IPC-6012 Minimum Ring RequirementA practical look at IPC-6012 annular ring minimums, the tolerance stack-ups behind them, and when high-reliability designs should exceed the spec.9 min read
- 3W Rule: Trace Separation = 3× Trace Width to Reduce Crosstalk3W Rule: Trace Spacing for Crosstalk ControlA practical guide to using S=3W trace spacing to control crosstalk, including differential pair exceptions, stackup effects, and when the rule stops being enough.11 min read
- Battery Management: Charge Path, Protection FET LayoutBattery Protection FET Layout & Charge Path DesignPractical PCB layout techniques for placing and routing battery protection FETs to balance thermal performance, EMI control, and charge-path efficiency.9 min read
- Surge Immunity: IEC 61000-4-5 Waveform and LevelIEC 61000-4-5 Surge: Waveform & Test LevelsA practical look at the 1.2/50 µs and 8/20 µs surge waveforms, test level selection, coupling modes, and the circuit and layout choices that determine pass or fail.10 min read
Medical Device Eng.34 articles
- Acoustic Properties of Tissue: Ultrasound Impedance, AttenuationUltrasound Impedance & Attenuation in TissueHow acoustic impedance mismatch creates ultrasound echoes, how attenuation limits depth, and why frequency choice trades resolution for penetration.9 min read
- Blood Glucose Reference Range: Fasting, Postprandial, HbA1cBlood Glucose Reference Ranges in Medical DevicesTranslates fasting, postprandial, and HbA1c glucose reference ranges into concrete sensor accuracy, lag-compensation, and calibration requirements for device engineers.10 min read
- Brain Waves: Delta, Theta, Alpha, Beta, Gamma EEG BandsEEG Brain Wave Bands: Delta, Theta, Alpha, Beta, GammaA practical guide to the five EEG frequency bands as clinical biomarkers, and the acquisition, filtering, and spectral analysis pipeline needed to extract them reliably.10 min read
- CT Hounsfield Units: Tissue Density ClassificationCT Hounsfield Units: Tissue Density ClassificationA practical breakdown of Hounsfield Units, tissue HU ranges, and the calibration factors engineers must control to keep CT reconstruction pipelines accurate.7 min read
- Cardiac Cycle: Systole, Diastole, Stroke Volume, Cardiac OutputCardiac Cycle: Systole, Diastole & OutputA clinically grounded walkthrough of systole, diastole, stroke volume, and cardiac output for engineers building pacemakers, monitors, and imaging systems.10 min read
- Coagulation: INR, PT, aPTT and Anticoagulation MonitoringCoagulation Tests: INR, PT, aPTT ExplainedHow the coagulation cascade produces PT, aPTT, and INR signals, and what that means for designing point-of-care anticoagulation monitoring devices.10 min read
- ECG Lead System: Einthoven Limb Leads, Chest Leads V1–V6ECG Lead System: Einthoven & Chest LeadsHow Einthoven's triangle, augmented limb leads, and V1-V6 chest electrodes combine into the 12-lead ECG, and what you give up with fewer channels.11 min read
- Galvanic Skin Response (GSR): Sympathetic Nervous IndicatorGSR Sensors: Measuring Sympathetic ActivationA practical guide to instrumenting galvanic skin response from electrode to firmware, covering sweat gland physiology, tonic/phasic signal decomposition, and hardware design trade-offs.10 min read
- Hemodynamics: Ohm's Law Analog (CO = MAP/SVR)Hemodynamics: Ohm's Law Analog (CO = MAP/SVR)How the Ohm's Law analog CO = MAP/SVR links cardiac output, blood pressure, and vascular resistance—and where it fails for real device design.10 min read
- Intracranial Pressure (ICP): Normal Range, MonitoringICP Monitoring: Normal Range & Clinical BasicsHow the skull's fixed volume turns small volume changes into dangerous pressure spikes, and what that means for ICP transducer and amplifier design.8 min read
- Korotkoff Sounds: Oscillometric BP Measurement PrincipleKorotkoff Sounds & Oscillometric BP MeasurementHow turbulent arterial flow produces Korotkoff sounds, how oscillometric devices sense the same event electronically, and where the two methods disagree.10 min read
- MRI Physics: Proton Spin, Larmor Frequency, T1/T2 RelaxationMRI Physics: Proton Spin & RelaxationA device-engineering grounding in proton spin, Larmor frequency, and T1/T2 relaxation—the physics behind every RF pulse, gradient waveform, and image contrast decision.10 min read
- Neonatal Monitoring Parameters: SpO2, HR, RR, Temp, BGNeonatal Vital Monitoring: SpO2, HR, RR, Temp, BGHow five vital signs — SpO2, HR, RR, temperature, and blood glucose — demand different sensor design and thresholds in newborns than in adults.11 min read
- Organ-on-Chip: Microfluidic Cell Culture and BiosensingOrgan-on-Chip: Microfluidic Culture & BiosensingHow embedded and analog engineers design the fluidic channels, electrodes, and signal chains that let organ-on-chip devices mimic real tissue physiology.10 min read
- Pharmacokinetics: Drug Absorption, Distribution, Metabolism, ExcretionPharmacokinetics: ADME in Medical Device DesignHow drug absorption, distribution, metabolism, and excretion timelines constrain sensor placement, calibration windows, and dosing algorithm thresholds.11 min read
- Pulse Wave Velocity (PWV) and Arterial StiffnessPulse Wave Velocity & Arterial Stiffness BasicsA foundational look at how arterial stiffness governs pulse wave velocity, the physics behind the Moens-Korteweg equation, and what it means for sensor and timing design in cardiovascular devices.8 min read
- Renal Biomarkers: GFR, Creatinine, BUN for Kidney FunctionRenal Biomarkers: GFR, Creatinine, BUNA practical guide to embedding creatinine, eGFR, and BUN into diagnostic algorithms for acute kidney injury detection and chronic kidney disease staging.10 min read
- Respiratory Physiology: Tidal Volume, RR, FRC, FVC, FEV1Respiratory Physiology: Tidal Volume, RR, FRC, FVC, FEV1The five respiratory parameters behind spirometer, ventilator, and wearable design, with clinical thresholds and sensor engineering trade-offs.11 min read
- X-Ray Interaction: Photoelectric Effect, Compton ScatteringX-Ray Interaction: Photoelectric Effect & Compton ScatteringA physics-first look at how photoelectric absorption and Compton scattering shape X-ray image contrast, scatter artifacts, and detector design choices.9 min read
- Temperature Sensor: NTC, RTD Pt100, Infrared ThermopileTemperature Sensors in Medical Devices: NTC, RTD, IRA practical comparison of NTC thermistors, RTD Pt100 sensors, and infrared thermopiles for medical-grade temperature measurement, from circuit design to firmware calibration.9 min read
- Biocompatibility: ISO 10993-1 Risk-Based Evaluation FrameworkISO 10993-1: Risk-Based Biocompatibility EvaluationA systematic walk through the ISO 10993-1 pyramid for scoping biocompatibility tests by contact type, duration, and material history.8 min read
- Design History File (DHF): Complete Development RecordDesign History File (DHF): Complete Development RecordHow to build and organize a Design History File that survives FDA inspection, with the records, traceability logic, and change control each phase requires.10 min read
- IEC 60601-1-2: EMC for Medical Electrical Equipment (4th Ed.)IEC 60601-1-2 (Ed. 4): EMC Requirements for Medical DevicesA practical walkthrough of IEC 60601-1-2 Edition 4 EMC requirements, from performance-level classification to enclosure design and technical file audits.12 min read
- Sterility Assurance Level (SAL): 10⁻⁶ for Sterile DevicesSterility Assurance Level (SAL) 10⁻⁶: Definition & ValidationA working engineer's guide to what SAL 10⁻⁶ actually proves, how sterilization validation protocols are built, and what design choices put it at risk.11 min read
- Sterilization: EO Gas, Gamma, E-Beam, Steam (Autoclave)Medical Device Sterilization Methods: EO, Gamma, E-Beam, SteamHow EO gas, gamma, e-beam, and steam autoclave sterilization each constrain material choice, electronics survival, and validation strategy.10 min read
- Accelerated Aging: ASTM F1980 Real-Time Equivalent CalculationASTM F1980 Accelerated Aging: Real-Time EquivalencyA step-by-step guide to the Arrhenius math behind ASTM F1980 shelf-life claims, plus the assumptions that cause real-time confirmation to fail.11 min read
- Creepage and Clearance: Function of Working Voltage and Pollution DegreeCreepage & Clearance: Voltage and Pollution RulesHow to turn working voltage, pollution degree, material group, and insulation class into exact creepage and clearance numbers that satisfy IEC 60601-1 audits.12 min read
- ESD Immunity: IEC 60601-1-2 Basic/Enhanced PerformanceESD Immunity Testing: IEC 60601-1-2 LevelsA practical guide to IEC 60601-1-2 ESD test levels, Basic vs Enhanced Performance classification, circuit protection design, and risk justification for notified body review.11 min read
- Electrical Protective Means: Double Insulation, Reinforced InsulationDouble & Reinforced Insulation in Medical DevicesA practical guide to choosing and validating double versus reinforced insulation under IEC 60601-1, covering testing, aging, and creepage/clearance trade-offs.10 min read
- Environmental Stress: Temperature, Humidity, Altitude (IEC 60068)IEC 60068 Environmental Stress Testing for Medical DevicesHow to design IEC 60068 environmental stress tests for medical devices that catch real failures and hold up under regulatory review.8 min read
- ISO 14971:2019 Scope and DefinitionsISO 14971:2019 Scope and DefinitionsA working guide to ISO 14971:2019's normative scope and definitions, showing where clinical, sensor, and biocompatibility data must feed the risk file.11 min read
- Isolation Barriers: Creepage, Clearance, Dielectric StrengthIsolation Barriers: Creepage, Clearance & Dielectric StrengthHow to design, route, and verify medical device isolation barriers so creepage, clearance, and dielectric strength hold up beyond minimum test voltage.11 min read
- Mechanical Safety: Drop, Vibration, Crush, Tip-Over TestMechanical Safety Testing for Medical DevicesTurn drop, vibration, crush, and tip-over hazards into testable pass/fail criteria tied directly to clinical risk in medical device design.11 min read
- Protective Earth (PE): Green/Yellow Wire, Continuity < 0.1 ΩProtective Earth (PE) Continuity Testing in Medical DevicesA practical breakdown of why the protective earth conductor must measure under 0.1 Ω, how to measure it correctly with four-wire technique, and how it fits into ISO 14971 risk management.12 min read
Control Systems13 articles
- Block Diagram Algebra: Series, Parallel, Feedback ReductionBlock Diagram Algebra: Series, Parallel & FeedbackMaster the series, parallel, and feedback reduction rules that collapse multi-loop block diagrams into a single closed-loop transfer function.10 min read
- Complementary Sensitivity T(s) = L(s)/(1+L(s))Complementary Sensitivity T(s): Tracking & StabilityHow T(s) = L(s)/(1+L(s)) predicts reference tracking, bandwidth, and overshoot, and why you can't minimize T(s) and S(s) at the same frequency.9 min read
- Disturbance Rejection: S(s) at Low FrequencyDisturbance Rejection: S(s) at Low FrequencyS(s) tells you exactly how much of a real-world disturbance survives to your output — here's the math, the trade-offs, and how to measure it.10 min read
- Final Value Theorem: lim(t→∞) y(t) = lim(s→0) sY(s)Final Value Theorem: Steady-State from Laplace DomainUse the Final Value Theorem to compute steady-state output and error directly from a transfer function, and learn exactly when the result can be trusted.10 min read
- First-Order Step Response: Rise Time, Settling TimeFirst-Order Step Response: Rise & Settling TimeClosed-form rise time and settling time formulas for first-order systems, with a scope-measurement procedure and worked numeric example.10 min read
- First-Order System: Time Constant τ, DC Gain KFirst-Order System: Time Constant τ and DC Gain KHow to read time constant τ and DC gain K from any first-order plant or circuit, and use them to predict real closed-loop control behavior.11 min read
- Initial Value Theorem: lim(t→0⁺) y(t) = lim(s→∞) sY(s)Initial Value Theorem in Control SystemsExtract a system's instantaneous startup value directly from its Laplace transform, and use it to catch improper transfer functions and bad pole-zero cancellations before simulating.10 min read
- Noise Amplification: T(s) at High FrequencyNoise Amplification at High Frequency in Feedback ControlWhy tighter feedback loops push T(s) toward 1 at high frequency, amplifying sensor noise, and how to shape loop gain without losing stability.10 min read
- Performance Specs: %OS, Ts, Tr, Tp, Ess (Steady-State Error)Control System Performance Specs: %OS, Ts, Tr, Tp, EssA practical breakdown of the five core control-loop performance specs—rise time, peak time, overshoot, settling time, and steady-state error—and how to trade them off.8 min read
- Second-Order Step Response: Overdamped, Critically, UnderdampedSecond-Order Step Response: Damping Modes ExplainedHow damping ratio ζ and natural frequency ωₙ determine whether a second-order system overshoots, rings, or crawls to steady state — with formulas and a worked RLC example.9 min read
- Second-Order System: ωn, ζ (Damping Ratio), ωdSecond-Order System: ωn, ζ, ωd ExplainedHow ωn, ζ, and ωd together set overshoot, settling time, and ringing in a second-order control loop, with a worked step-response measurement.11 min read
- Steady-State Error: Position, Velocity, Acceleration Error ConstantsSteady-State Error Constants: Kp, Kv, KaHow to derive position, velocity, and acceleration error constants from an open-loop transfer function and use them to hit steady-state error specs.9 min read
- Transfer Function G(s): Definition and DerivationTransfer Function G(s): Definition and DerivationHow transfer function G(s) turns differential equations into algebra, and how poles, zeros, and DC gain predict stability and steady-state error.10 min read
Instrumentation & Measurement7 articles
- Humidity Sensor: Capacitive, Resistive, PsychrometricHumidity Sensors: Capacitive, Resistive & PsychrometricA comparison of how capacitive, resistive, and psychrometric humidity sensors work, their signal conditioning needs, and how to choose between them.11 min read
- Load Cell: Types (Shear, Bending, Column), Rated OutputLoad Cell Types & Rated Output ExplainedA ground-up comparison of shear beam, bending beam, and column load cells, plus how rated output in mV/V shapes signal conditioning and system accuracy.9 min read
- Pressure Sensor: Capacitive, Piezoresistive, ResonantPressure Sensors: Capacitive, Piezoresistive, ResonantA comparison of capacitive, piezoresistive, and resonant pressure sensing - the physics behind each, their signal conditioning needs, and how to pick the right one.9 min read
- Wheatstone Bridge: Balance, Sensitivity, Temperature Comp.Wheatstone Bridge: Balance, Sensitivity & Temperature CompensationA practical walkthrough of Wheatstone bridge balance, sensitivity, and temperature compensation for engineers building strain gauge and transducer readout chains.12 min read
- Predictive Maintenance: Vibration Trend, Corrosion MonitorPredictive Maintenance: Vibration & Corrosion MonitoringHow trending vibration spectra and corrosion rates—not single readings—exposes bearing wear, misalignment, and wall loss weeks before failure.10 min read
- Vibration Monitoring: Velocity, Acceleration, Proximity ProbeVibration Monitoring: Velocity, Acceleration & Proximity ProbesA practical comparison of accelerometers, velocity transducers, and eddy-current proximity probes for vibration-based predictive maintenance.10 min read
- Smart Sensor: IEEE 1451, TEDS (Transducer Electronic Data Sheet)IEEE 1451 & TEDS: Smart Sensor Plug-and-PlayHow IEEE 1451 and TEDS move sensor calibration and identification off paper and into nonvolatile memory, enabling true plug-and-play measurement systems.10 min read
IoT & Connectivity36 articles
- Asset Tracking: Real-Time Location System (RTLS)Asset Tracking: Real-Time Location System (RTLS)How RTLS turns radio timing, angle, and signal-strength measurements into continuous, sub-meter indoor asset positions — and how to size a real deployment.7 min read
- Automotive IoT: V2X, OBD-II Telematics, Fleet ManagementAutomotive IoT: V2X, OBD-II Telematics, Fleet ManagementHow V2X sidelink radios, OBD-II/J1939 telematics, and fleet cloud pipelines each solve a different latency and bandwidth problem in connected vehicles.9 min read
- Connected Health IoT: Wearables, Remote MonitoringConnected Health IoT: Wearables, Remote MonitoringHow wearables and remote patient monitoring turn biosignals into reliable, compliant IoT data — from sensor front ends through BLE link budgets to alarm delivery.6 min read
- Constrained Devices: RFC 7228 Class 0, 1, 2 DefinitionsConstrained Devices: RFC 7228 Class 0, 1, 2 DefinitionsRFC 7228's Class 0/1/2 memory boundaries decide whether a node needs a gateway, can run CoAP/DTLS itself, or can host a near-standard TLS stack.6 min read
- Device Lifecycle: Provisioning, Operation, Update, DecommissionDevice Lifecycle: Provisioning, Operation, Update, DecommissionHow IoT devices should be engineered to move safely through provisioning, operation, firmware updates, and decommissioning at fleet scale, from bench to teardown.7 min read
- Edge vs. Fog vs. Cloud Processing: Latency Trade-offEdge vs. Fog vs. Cloud Processing: Latency Trade-offHow to split IoT processing across edge, fog, and cloud tiers based on latency deadlines, bandwidth cost, and a worked factory motor-protection example.9 min read
- Energy Management IoT: Sub-Metering, BEMS IntegrationEnergy Management IoT: Sub-Metering, BEMS IntegrationHow circuit-level sub-metering and BEMS integration turn raw utility bills into actionable, per-load energy data — with a worked demand-charge example.14 min read
- Environmental Monitoring: Air Quality, Water, NoiseEnvironmental Monitoring: Air Quality, Water, NoiseHow air, water, and noise IoT nodes actually measure their targets — sensor physics, calibration math, and the data architecture that makes readings trustworthy.6 min read
- Industrial IoT (IIoT) vs. Consumer IoT DifferencesIndustrial IoT (IIoT) vs. Consumer IoT DifferencesIIoT and consumer IoT share the same acronym but opposite priorities: reliability and determinism vs. cost and convenience. Here's what actually differs, quantified.6 min read
- IoT Business Models: SaaS, DaaS, Platform-as-a-ServiceIoT Business Models: SaaS, DaaS, Platform-as-a-ServiceHow SaaS, DaaS, and PaaS revenue models translate into concrete hardware trade-offs — BOM cost, OTA maturity, battery life, and field-service design.12 min read
- IoT Data Flow: Telemetry, Command, Alarm, ConfigIoT Data Flow: Telemetry, Command, Alarm, ConfigIoT systems carry four distinct message types—telemetry, command, alarm, and config—each needing different latency, reliability, and QoS treatment.7 min read
- IoT Data Formats: JSON, CBOR, MessagePack, ProtobufIoT Data Formats: JSON, CBOR, MessagePack, ProtobufCompares JSON, CBOR, MessagePack and Protobuf for IoT payloads — encoding size, parse cost, schema trade-offs, and a worked byte-by-byte example.7 min read
- IoT Definition: Sensors + Connectivity + Cloud + AnalyticsIoT Definition: Sensors + Connectivity + Cloud + AnalyticsA precise, four-layer engineering definition of IoT — sensors, connectivity, cloud, analytics — with the trade-offs and a worked cold-chain power budget.7 min read
- IoT Device Classification: Constrained, Gateway, CloudIoT Device Classification: Constrained, Gateway, CloudHow constrained sensors, gateways, and cloud services divide IoT system responsibilities — with a worked battery-life calculation and design trade-offs for each tier.6 min read
- IoT Device Management: Registration, Monitoring, OTAIoT Device Management: Registration, Monitoring, OTAHow registration, monitoring, and OTA updates work together to keep large IoT fleets secure, observable, and maintainable long after deployment ships.7 min read
- IoT Ecosystem: Devices, Gateways, Brokers, AppsIoT Ecosystem: Devices, Gateways, Brokers, AppsA breakdown of the four-layer IoT structure — devices, gateways, brokers, applications — with sizing math, QoS tradeoffs, and the failure modes that sink deployments at scale.6 min read
- IoT ROI Calculation: Cost Savings, Efficiency MetricsIoT ROI Calculation: Cost Savings, Efficiency MetricsA practical framework for building a defensible IoT ROI case: cost/benefit structure, efficiency metrics, payback period, and a fully worked predictive-maintenance example.6 min read
- IoT Scalability: Millions of Devices, Message BrokersIoT Scalability: Millions of Devices, Message BrokersHow IoT platforms scale from thousands to millions of devices: connection limits, thundering herds, broker clustering, and message-queue decoupling, with a worked sizing example.12 min read
- Open Connectivity Foundation (OCF) IoTivity StandardOpen Connectivity Foundation (OCF) IoTivity StandardHow OCF's resource model and IoTivity's CoAP-based implementation standardize device interoperability — and where they still fit next to Matter.5 min read
- Regulatory Landscape: FCC, CE, ETSI EN 303 645 IoTRegulatory Landscape: FCC, CE, ETSI EN 303 645 IoTHow FCC, CE marking, and ETSI EN 303 645 shape RF certification and security requirements for connected embedded products — and where they now overlap.7 min read
- Retail IoT: Smart Shelf, Inventory, Customer AnalyticsRetail IoT: Smart Shelf, Inventory, Customer AnalyticsHow smart shelves, RFID inventory, and Wi-Fi/BLE customer analytics actually work — with a load-cell sensitivity budget and the trade-offs that decide which sensing method fits which SKU.7 min read
- Smart Agriculture IoT: Sensors, Drones, AutomationSmart Agriculture IoT: Sensors, Drones, AutomationHow soil, weather, and canopy sensors combine with drone imagery and LPWAN links to close real irrigation and variable-rate automation loops in the field.7 min read
- Supply Chain IoT: RFID, GPS, Condition MonitoringSupply Chain IoT: RFID, GPS, Condition MonitoringHow RFID, GPS/GNSS, and condition sensors combine in supply chain IoT — with reporting-budget and battery-life math for a cold-chain tracking example.6 min read
- Sustainability IoT: Carbon Footprint, Green IoT DesignSustainability IoT: Carbon Footprint, Green IoT DesignA quantitative look at where IoT carbon footprint actually comes from — embodied vs. operational energy — with a worked device energy budget and ranked design levers.6 min read
- Time-Series Data: Characteristics and Storage NeedsTime-Series Data: Characteristics and Storage NeedsWhy sensor telemetry needs different storage than relational data, how compression cuts raw volume by 10–100×, and how to size and retain it correctly.6 min read
- Thread Border Router: External IP to Thread Network BridgeThread Border Router: Bridging External IP NetworksHow a Thread Border Router bridges 6LoWPAN mesh and IPv6 networks, covering commissioning, hardware platforms, redundancy, and latency trade-offs.10 min read
- AWS IoT Core: MQTT Broker, Rules, Shadow, Fleet ProvisioningAWS IoT Core: MQTT, Rules, Shadow & Fleet ProvisioningA practical walkthrough of how AWS IoT Core's MQTT broker, Rules Engine, Device Shadow, and Fleet Provisioning combine to solve authentication, sync, and onboarding at scale.10 min read
- Azure Digital Twins: DTDL Model, Graph, Event RoutesAzure Digital Twins: DTDL, Graph & Event RoutesHow Azure Digital Twins combines DTDL modeling, a queryable relationship graph, and event routes to turn raw IoT telemetry into a live, event-driven system representation.9 min read
- Azure IoT Hub: Device Provisioning, Cloud-to-Device, TwinAzure IoT Hub: Device Provisioning, C2D, TwinHow Azure IoT Hub's DPS, cloud-to-device messaging, and device twins work together to onboard, command, and track fleets of devices in production.9 min read
- Device Identity: X.509 Certificate, Pre-Shared Key (PSK)Device Identity: X.509 vs. PSK for IoT AuthA practical comparison of X.509 certificates and pre-shared keys for IoT device identity, covering storage, power impact, lifecycle management, and hybrid deployment patterns.10 min read
- ETSI EN 303 645: Cybersecurity for Consumer IoT BaselineETSI EN 303 645: IoT Security Baseline RequirementsA practical breakdown of ETSI EN 303 645's device-level security baselines, from password provisioning to OTA updates, mapped across IoT architecture layers and device classes.9 min read
- Energy Harvesting: Solar, TEG, RF, Vibration for IoTEnergy Harvesting for IoT: Solar, TEG, RF & VibrationA field-level comparison of solar, TEG, RF, and vibration harvesting for IoT, with power budgets, power management circuits, and hybrid buffering strategies.9 min read
- Low-Power Design: RTC Wake, Interrupt-Driven, TicklessLow-Power Design: RTC Wake, Interrupt-Driven, TicklessHow RTC timing, event-driven execution, and tickless kernels combine to let constrained IoT devices sleep over 99.9% of the time without losing responsiveness.12 min read
- Vulnerability Disclosure: CVE, Coordinated Disclosure PolicyCVE & Coordinated Disclosure for IoT SecurityHow CVE identifiers, coordinated disclosure timelines, and vendor policy frameworks apply to distributed IoT systems with constrained, long-lived devices.9 min read
- Precision Agriculture: UAV, Satellite, Ground Sensor FusionSensor Fusion in Precision Agriculture: UAV–Satellite–Ground IntegrationHow to architect IoT systems that fuse satellite, UAV, and ground sensor data into one coherent precision agriculture workflow despite mismatched latency, bandwidth, and power constraints.10 min read
- Remote Patient Monitoring (RPM): BLE Hub to EHRRPM BLE Hub to EHR: End-to-End ArchitectureA systems view of remote patient monitoring: from BLE wearable to hub to FHIR-normalized EHR record, with the protocol and compliance trade-offs at each hop.11 min read
VLSI & Semiconductor7 articles
- Avalanche Breakdown: Impact Ionization CoefficientAvalanche Breakdown & Impact Ionization CoefficientHow accelerated carriers trigger avalanche breakdown, and how the impact ionization coefficient lets engineers predict breakdown voltage across materials and temperature.8 min read
- Carrier Concentration: n and p in Thermal EquilibriumCarrier Concentration n and p in Thermal EquilibriumA grounded walkthrough of equilibrium electron and hole concentrations, the mass action law, and Fermi level position that underlies every semiconductor device model.9 min read
- Drive Strength: X1, X2, X4, X8, X16 Cell VariantsDrive Strength Variants: X1, X2, X4, X8, X16 ExplainedHow X1 through X16 standard cell variants scale transistor width to trade timing against area, power, and leakage, and how to pick the right strength without over-designing.11 min read
- Pipeline Design: Stage Balancing, Retiming, Stall/FlushPipeline Stage Balancing & Retiming for VLSIA practical guide to balancing pipeline stages, applying retiming correctly, and implementing stall and flush logic without deadlocks or timing surprises.11 min read
- Standard Cell Library: INV, BUF, NAND2, NOR2, MUX2, DFFStandard Cell Library: Core Logic Gates & Flip-FlopsA practical look at why INV, NAND2, MUX2, and DFF cells are shaped the way they are, and how to read Liberty files for timing closure decisions.13 min read
- Parasitic Extraction: StarRC, Quantus RC ExtractionParasitic Extraction: StarRC & Quantus RCA practical look at StarRC and Quantus RC extraction flows, SPEF coupling, and the tool trade-offs that determine whether a design closes timing at silicon.10 min read
- Package Stress: CTE Mismatch, Warpage, Solder JointPackage Stress: CTE Mismatch & Solder Joint ReliabilityWhy packages crack under thermal cycling, how engineers model and measure warpage, and which material stack-ups keep solder joints alive for decades.16 min read
Firmware & Software Eng.14 articles
- Agile Methodology: Sprint, Backlog, Scrum, KanbanAgile in Firmware: Sprint, Backlog, Scrum, KanbanHow embedded teams adapt Scrum, Kanban, and backlog practices to hardware dependencies, test gates, and resource-constrained targets.8 min read
- Change Control Board (CCB): Impact Analysis, ApprovalChange Control Board: Impact Analysis & ApprovalHow to structure CCB impact analysis and approval workflows that catch firmware regressions early without slowing iteration to a crawl.9 min read
- Software Architecture: Monolith, Layered, MicrokernelSoftware Architecture Patterns for Embedded SystemsA comparison of monolithic, layered, and microkernel firmware architectures across memory footprint, real-time latency, and long-term maintainability.10 min read
- Technical Debt: Identification, Quantification, ReductionTechnical Debt in Embedded Systems: Identify & ReduceIn embedded systems technical debt isn't just messy code—it drives field failures and warranty cost. Here's how to find it, measure it, and pay it down safely.10 min read
- Interrupt Latency: Worst-Case Interrupt Response TimeInterrupt Latency: Worst-Case Response TimeA practical breakdown of interrupt latency's components, measurement methods, and optimization techniques for engineers who need provable worst-case numbers, not averages.9 min read
- Priority Inversion: Mars Pathfinder Bug Case StudyPriority Inversion: Mars Pathfinder Bug Case StudyHow an unprotected mutex nearly ended the Mars Pathfinder mission, and what priority inheritance and ceiling protocols do to stop it happening in your firmware.10 min read
- Delta OTA: Binary Diff (bsdiff, VCDIFF) for Tiny PayloadsDelta OTA: Binary Diff for Tiny PayloadsHow bsdiff and VCDIFF binary diffing cut embedded OTA payloads by 80-95%, and how to generate, apply, and sign deltas safely on constrained devices.11 min read
- CAN Bus: Frame Format, Arbitration, Bit StuffingCAN Bus Frame Format, Arbitration & Bit StuffingA bit-level walkthrough of CAN frame structure, non-destructive arbitration, and bit stuffing for engineers debugging real-time automotive and industrial firmware.11 min read
- CAN FD: Faster Data Phase, Up to 64 Byte PayloadCAN FD: 64-Byte Payload & Faster Data PhaseHow CAN FD's dual bitrate data phase and 64-byte payloads work, plus the firmware gotchas in DLC encoding, CRC checking, and mixed-network migration.12 min read
- CANopen: DS301 Object Dictionary, NMT, PDO, SDOCANopen DS301: Object Dictionary, NMT, PDO, SDOA practical guide to CANopen DS301's Object Dictionary, NMT state machine, PDO cyclic transfers, and SDO configuration for building deterministic embedded networks.11 min read
- Environmental Testing: Temp Cycling, Humidity, VibrationEnvironmental Testing in Firmware: Temp, Humidity, VibrationHow to design temperature cycling, humidity, and vibration tests that catch firmware faults the bench never reproduces, with instrumentation and traceability methods.13 min read
- Integration Test: Module Interaction on Real or Simulated HWIntegration Testing: Module Interaction on Real & Simulated HardwareHow to design, automate, and debug integration tests that catch timing, interface, and resource bugs across firmware modules on real or simulated hardware.11 min read
- Regression Testing: Automated Nightly Suite on CIRegression Testing: Automated Nightly Suite on CIA guide to structuring an overnight regression suite for embedded firmware: test layering, HIL vs simulation, flaky test mitigation, and failure triage workflows.9 min read
- Time Synchronization: gPTP (IEEE 802.1AS) in AutomotivegPTP (IEEE 802.1AS) Time Sync in AutomotiveHow IEEE 802.1AS gPTP delivers microsecond-level clock synchronization across automotive Ethernet ECUs, and why CAN-based timing can't meet ADAS safety requirements.11 min read
VLSI & Chip Design2 articles
- Short-Channel Effects: DIBL, Velocity SaturationShort-Channel Effects: DIBL & Velocity SaturationWhy smaller transistors leak more and drive less current than square-law theory predicts, and the design techniques that keep DIBL and velocity saturation in check.10 min read
- Temperature Compensation: CTAT and PTATTemperature Compensation: CTAT and PTAT CircuitsHow CTAT and PTAT current sources cancel each other's temperature drift to build stable analog references, with a worked PTAT derivation and layout guidance.8 min read
Embedded & Firmware14 articles
- ARM Cortex-M Pipeline Stages (M0 to M55)ARM Cortex-M Pipeline Stages: M0 to M55Why Pipeline Architecture Matters in Embedded Systems Every Cortex-M core executes instructions through a pipeline — a hardware assembly line that overlaps fetch, decode, and exec...11 min read
- Bit-Field Struct for Register MappingBit-Field Structs for MCU Register MappingA practical guide to using bit-field structs for register mapping in embedded C, covering syntax, volatile qualification, portability pitfalls, and when CMSIS is the safer choice.8 min read
- C Language Basics: Pointers, Structs, UnionsC Pointers, Structs & Unions for EmbeddedThe pointer, struct, and union patterns every MCU datasheet assumes you already know, from register overlays to padding, volatile, and strict aliasing.10 min read
- C const and restrict for Optimization HintsC const and restrict: Compiler Optimization HintsA practical guide to using const and restrict in embedded C to unlock compiler optimizations, reduce code size, and speed up critical loops without platform hacks.8 min read
- Cortex-M55 Helium MVE Vector InstructionsCortex-M55 Helium MVE Vector InstructionsA practical tour of Cortex-M55 Helium MVE: writing intrinsics, predicated loops, auto-vectorization limits, and what happens to vector state during interrupts.11 min read
- Function Pointers and Callback PatternFunction Pointers & Callbacks in Embedded CHow function pointers and callbacks decouple firmware drivers from application logic, with context passing, ISR safety, and Cortex-M performance trade-offs.12 min read
- Memory Footprint OptimizationMemory Footprint Optimization in Embedded SystemsPractical techniques for fitting firmware into tight Flash and SRAM budgets, from struct layout and compiler flags to const placement and build-time size tracking.11 min read
- NVIC: Priority Grouping, Preemption, Sub-PriorityNVIC Priority Grouping, Preemption & Sub-PriorityHow to split the NVIC priority field between preemption and sub-priority, configure PRIGROUP correctly, and debug preemption that isn't behaving as expected.9 min read
- Processor Operating Modes: Thread, HandlerThread vs Handler Mode in ARM Cortex-MWhy Cortex-M automatically switches between Thread and Handler Mode, what that means for stack pointers and privilege, and how to detect the current mode in firmware.9 min read
- Program Counter, Stack Pointer, Link RegisterProgram Counter, Stack Pointer, Link RegisterHow PC, SP, and LR coordinate function calls and returns on ARM Cortex-M, and how to read them when debugging a crash or writing RTOS-aware code.12 min read
- Register-Level Peripheral Access via CMSISRegister-Level Peripheral Access via CMSISHow CMSIS standardizes peripheral register access on Cortex-M devices, from base-address typedefs to volatile semantics and safe read-modify-write patterns.9 min read
- Static, Inline, and Extern LinkageStatic, Inline, and Extern Linkage in Embedded CA practical guide to static, extern, and inline linkage in embedded C, covering symbol visibility, code size trade-offs, and common linker errors.10 min read
- SysTick Timer ConfigurationSysTick Timer Configuration on ARM Cortex-MA register-level guide to configuring Cortex-M SysTick for a reliable 1 ms system tick, covering reload math, interrupt handlers, and common misconfigurations.11 min read
- PWM Output: Timer Configuration, ResolutionPWM Output: Timer Configuration & ResolutionA practical workflow for turning PWM frequency and resolution requirements into prescaler, ARR, and CCR register values, with the math worked out.10 min read
Power Electronics & EE1 article
DSP & Signal Processing4 articles
- Fourier Transform: Definition and PropertiesFourier Transform: Definition and PropertiesA ground-up look at the Fourier Transform's math, properties, symmetry, and boundary effects, connecting continuous theory to DFT implementation.9 min read
- Bessel Filter: Maximally Flat Group DelayBessel Filter: Maximally Flat Group DelayHow Bessel filters achieve maximally flat group delay to preserve pulse shape and timing, and why that costs magnitude roll-off steepness.11 min read
- Acoustic Echo Cancellation (AEC) with LMSAcoustic Echo Cancellation with LMS AlgorithmWhy naive LMS echo cancellers diverge on real voice calls, and how step size tuning, NLMS normalization, and double-talk detection fix it in embedded systems.11 min read
- Double-Talk Detection in AECDouble-Talk Detection in AECHow production AEC systems detect double-talk using ERLE, Geigel thresholds, and spectral analysis to stop adaptive filters from diverging.12 min read
Hardware HW Engineer4 articles
- 3D Model Assignment for Component3D Model Assignment for ComponentsA practical walkthrough of sourcing, validating, and linking 3D component models to PCB footprints so mechanical design flaws surface in review, not in the lab.9 min read
- Alternative Component Cross-ReferenceAlternative Component Cross-ReferenceA practical, systematic approach to finding and validating alternative components without compromising electrical, mechanical, or supply-chain integrity.7 min read
- BGA Breakout: Dog-Bone, Via-in-Pad TechniquesBGA Breakout: Dog-Bone & Via-in-Pad RoutingA practical comparison of dog-bone and via-in-pad BGA escape routing, covering stub resonance, via fill risks, and how to assign breakout method by signal type.11 min read
- Signal Return Path: Ground Plane ContinuityGround Plane Continuity & Return PathsA practical guide to maintaining ground plane continuity, placing stitching vias, and bridging plane splits so return currents stay low-inductance.10 min read
Radar & RF Systems1 article
Biomedical & Med Device5 articles
- Accelerometer for Activity and Fall DetectionAccelerometer for Activity and Fall DetectionA practical guide to building a fall detection wearable, from accelerometer range and sampling rate through threshold algorithms, power budgeting, and clinical validation.10 min read
- Analog Front-End Power Budget for WearableAnalog Front-End Power Budget for WearablesA practical guide to estimating and optimizing analog front-end power in wearable biopotential devices, from datasheet interpretation to field validation.11 min read
- Body Temperature: IR Thermopile CircuitIR Thermopile Circuit for Body Temperature SensingA practical guide to amplifying nano/microvolt thermopile signals, compensating the cold junction, and correcting emissivity and drift for accurate body temperature sensing.11 min read
- ECG AFE: ADS1291, MAX30003, AD8232ECG AFE Comparison: ADS1291, MAX30003, AD8232A system-level comparison of the ADS1291, MAX30003, and AD8232 ECG analog front-ends, covering RLD, power budgets, and leads-off detection trade-offs.11 min read
- Electrical Safety: Protective Earth, LeakageProtective Earth & Leakage Current in Medical DevicesA practical guide to translating IEC 60601-1 protective earth and leakage current requirements into verifiable design specifications and test evidence.11 min read
Precision Ag Embedded2 articles
- Animal Welfare and Precision Livestock FarmingAnimal Welfare in Precision Livestock FarmingAn engineering look at how wearable sensors, analog front-ends, and wireless protocols combine to detect livestock heat stress and illness before visible symptoms appear.8 min read
- Vegetation Indices: NDVI, EVI, NDWI, SAVIVegetation Indices for Precision Ag: NDVI, EVI, NDWI, SAVIA field-engineering guide to calculating and interpreting NDVI, EVI, NDWI, and SAVI from multispectral sensor data for stress detection and input decisions.9 min read
PLC & DCS & SCADA4 articles
- Actuators: Control Valves, Dampers, Pumps, MOVsActuators in PLC/DCS/SCADA SystemsHow PLC/DCS systems command control valves, dampers, pumps, and MOVs, and why actuator response time and deadband shape closed-loop control performance.11 min read
- Chromatograph and Analyzer System InterfaceChromatograph & Analyzer System InterfaceA practical guide to interfacing chromatographs and analyzers with PLC/DCS systems, covering signal types, wiring, scaling, and alarm integration.9 min read
- Solenoid Valve: DC/AC, Single/Double EnergizeSolenoid Valve Types: DC/AC & Single/Double EnergizeHow solenoid valve energization type and architecture drive SIL rating, diagnostic coverage, and proof-test strategy in safety instrumented systems.9 min read
- Digital Twin Platform: Azure DT, MindSphereDigital Twin Platforms: Azure DT vs MindSphereA practical comparison of Azure Digital Twins and MindSphere for PLC/DCS/SCADA engineers, covering integration patterns, latency limits, and brownfield rollout strategy.9 min read
Soldering9 articles
- Bare Board Incoming Inspection per IPC-A-600Bare Board Incoming Inspection per IPC-A-600A practical walkthrough of IPC-A-600 bare board incoming inspection: defects to check, class selection, test methods, and disposition before parts ever touch the board.8 min read
- IPC-7711/7721: Rework, Modification, and Repair StandardIPC-7711/7721: Rework & Hand Soldering RulesIPC-7711/7721 turns rework workmanship into measurable iron temperatures, dwell times, and inspection criteria that protect reliability.10 min read
- Post-Rework Cleaning: Isopropyl Alcohol (IPA) 99%IPA 99% Post-Rework Cleaning: Flux Removal & ProcessPractical rules for IPA 99% post-rework cleaning: timing, technique, drying control, and storage to prevent white residue and ionic bridging under dense components.11 min read
- Reflow Profile: Ramp Rate Limits (°C/sec) per J-STD-020Reflow Ramp Rate Limits per J-STD-020How to read, measure, and tune J-STD-020 ramp rate limits across reflow zones to prevent tombstoning, balling, and hidden BGA micro-cracking.8 min read
- Functional Test (FT): Board-Level Functionality TestBoard-Level Functional Test (FT) StrategyHow to design board-level functional test to catch what solder inspection misses, verify voltage and current margins, and diagnose failures back to their root cause.12 min read
- IPC-A-610: Acceptability of Electronic AssembliesIPC-A-610: Acceptability Standards for Solder JointsHow IPC-A-610 turns solder joint inspection into repeatable, classifiable criteria across manual, AOI, and X-ray methods.9 min read
- Visual Inspection: Magnifier and Stereo MicroscopeVisual Inspection: Magnifier and Stereo MicroscopeHow to select magnifiers and stereo microscopes for solder joint inspection, what defects they catch, and when to hand off to AOI or X-ray.10 min read
- X-Ray Inspection: BGA and QFN Void AnalysisX-Ray Void Analysis in BGA and QFN Solder JointsPractical guidance for setting void acceptance limits, tuning AXI sensitivity, and connecting X-ray void data to field reliability in BGA and QFN joints.13 min read
- IPC-J-STD-001: Requirements for Soldering Electrical AssembliesIPC-J-STD-001: Soldering Assembly StandardsA practical breakdown of IPC-J-STD-001 requirements into the process decisions, defect calls, and operator qualifications that run an assembly floor.11 min read